Department of Computer Engineering2024-11-0920030-7695-2003-010.1109/DSD.2003.12319032-s2.0-84944324519http://dx.doi.org/10.1109/DSD.2003.1231903https://hdl.handle.net/20.500.14288/15007Double precision floating-point arithmetic is inadequate for many scientific computations. This paper presents the design of a quadruple precision floating-point multiplier that also supports two parallel double precision multiplications. Since hardware support for quadruple precision arithmetic is expensive, a new technique is presented that requires much less hardware than a fully parallel quadruple precision multiplier With this implementation, quadruple precision multiplication has a latency of three cycles and two parallel double precision multiplications have a latency of only two cycles. The design is pipelined so that two double precision multiplications can be started every cycle or a quadruple precision multiplication can be started every other cycle.Computer scienceHardware architectureConference proceeding18551210001180