2024-11-092006978-1-4244-0784-21058-639310.1109/aCSSC.2006.3550502-s2.0-47049087676http://dx.doi.org/10.1109/aCSSC.2006.355050https://hdl.handle.net/20.500.14288/12948Many scientific applications require more accurate computations than double precision or double-extended precision floating-point arithmetic. This paper presents the design of a dual-mode quadruple precision floating-point divider that also supports two parallel double precision division. A radix- 4 SRT division algorithm with minimal redundancy is used to implement the dual-mode quadruple precision floating-point divider. To estimate area and worst case delay, a double, a quadruple, a dual-mode double, and a dual-mode quadruple precision floating-point division units are implemented in VHDL and synthesized. The synthesis results show that the dual-mode quadruple precision divider requires 22% more area than the quadruple precision divider and the worst case delay is 1% longer. A quadruple precision division takes fifty nine cycles and two parallel double precision division take twenty nine cycles.EngineeringElectrical and electronic engineeringImaging sciencePhotographic technologyTelecommunicationsConference proceeding246925203068N/A3804