Design rule-compliant inverse design for silicon photonics using deep generative networks with embedded length-scale constraints

Abstract

We present a deep learning-based inverse design framework for silicon photonics that inherently enforces strict CMOS foundry design rule constraints, including minimum feature sizes and spacing. Our generator network uses seven specialized resize-convolution layers trained with custom design rule losses, producing fabrication-ready device geometries with well defined material boundaries. Applied to a 50/50 power splitter, the method achieved a loss of 2.8x10(-4) in 149 iterations, outperforming pixel-based approaches that require over 800 iterations and often violate constraints. This approach enables fast, high-fidelity, length-scale-constrained topology optimization, marking a significant advance toward practical, fabrication-compatible inverse design in silicon photonics.