Researcher:
Küçükkabak, Umut

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Master Student

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Umut

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Küçükkabak

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Küçükkabak, Umut

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2004 - 20052

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Researcher Of Publications: search.filters.isAuthorOfPublication.98397acd-ca4c-46c7-a476-9c9e8a27a4cf

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    A combined interval and floating-point reciprocal unit
    (IEEE, 2005) N/A; N/A; Department of Computer Engineering; Küçükkabak, Umut; Akkaş, Ahmet; Master Student; Faculty Member; Department of Computer Engineering; Graduate School of Sciences and Engineering; College of Engineering; N/A
    Interval arithmetic is one technique for accurate and reliable computing. Among interval arithmetic operations, division is the most time consuming operation. This paper presents the design and implementation of a combined interval and floating-point reciprocal unit. To compute the reciprocal of an operand, an initial approximation is computed first and then iterated twice by Newton-Raphson iteration. The combined interval and floating-point reciprocal unit computes the reciprocal of a double precision floating-point number in eleven clock cycles and the reciprocal of an interval in twenty-one clock cycles. The unit is implemented in VHDL and synthesized to estimate the area and the worst case delay. Simulation results showed that the least significant bit of the floating-point result cannot be guaranteed to be same for all cases compared to the result based on an infinite precision. For interval reciprocal, however, the true result is contained in the result interval.
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    Design and implementation of reciprocal unit using table look-up and newton-raphson iteration
    (IEEE Computer Soc, 2004) N/A; N/A; Department of Computer Engineering; Küçükkabak, Umut; Akkaş, Ahmet; Master Student; Faculty Member; Department of Computer Engineering; Graduate School of Sciences and Engineering; College of Engineering; N/A
    Combination of initial approximation through a table look-up and Newton-Raphson iteration is an effective way to compute reciprocal, which may replace the division operation. This paperpresents the design and implementation of reciprocal unit, which computes the reciprocal of double precision of floating-point number in eleven clock cycles. The presented design ultilizes a 2(10) x 20 bits ROM followed by two Newton-Raphson iterations. The design is implemented in VHDL and synthesized to estimate the area and the worst case delay Simulation results show that the least significand bit of the result cannot be guaranteed to be correct for all cases.