Publication: Automated and modular refinement reasoning for concurrent programs
dc.contributor.coauthor | Hawblitzel, Chris | |
dc.contributor.coauthor | Petrank, Erez | |
dc.contributor.coauthor | Qadeer, Shaz | |
dc.contributor.department | Department of Computer Engineering | |
dc.contributor.kuauthor | Taşıran, Serdar | |
dc.contributor.kuprofile | Faculty Member | |
dc.contributor.other | Department of Computer Engineering | |
dc.contributor.schoolcollegeinstitute | College of Engineering | |
dc.contributor.yokid | N/A | |
dc.date.accessioned | 2024-11-09T23:59:52Z | |
dc.date.issued | 2015 | |
dc.description.abstract | We present CIVL, a language and verifier for concurrent programs based on automated and modular refinement reasoning. CIVL supports reasoning about a concurrent program at many levels of abstraction. Atomic actions in a high-level description are refined to fine-grain and optimized lower-level implementations. A novel combination of automata theoretic and logic-based checks is used to verify refinement. Modular specifications and proof annotations, such as location invariants and procedure pre- and post-conditions, are specified separately, independently at each level in terms of the variables visible at that level. We have implemented CIVL as an extension to the BOOGIE language and verifier. We have used CIVL to refine a realistic concurrent garbage collection algorithm from a simple high-level specification down to a highly-concurrent implementation described in terms of individual memory accesses. | |
dc.description.indexedby | WoS | |
dc.description.indexedby | Scopus | |
dc.description.openaccess | NO | |
dc.description.publisherscope | International | |
dc.description.volume | 9207 | |
dc.identifier.doi | 10.1007/978-3-319-21668-3_26 | |
dc.identifier.eissn | 1611-3349 | |
dc.identifier.isbn | 978-3-319-21668-3 | |
dc.identifier.isbn | 978-3-319-21667-6 | |
dc.identifier.issn | 0302-9743 | |
dc.identifier.quartile | Q4 | |
dc.identifier.scopus | 2-s2.0-84951179627 | |
dc.identifier.uri | http://dx.doi.org/10.1007/978-3-319-21668-3_26 | |
dc.identifier.uri | https://hdl.handle.net/20.500.14288/15715 | |
dc.identifier.wos | 491470400026 | |
dc.keywords | Verification | |
dc.keywords | Reduction | |
dc.keywords | Proofs | |
dc.language | English | |
dc.publisher | Springer International Publishing Ag | |
dc.source | Computer Aided Verification, Cav 2015, Pt II | |
dc.subject | Computer science | |
dc.subject | Software engineering | |
dc.subject | Computer science-mathematics | |
dc.subject | Electrical electronics engineering | |
dc.title | Automated and modular refinement reasoning for concurrent programs | |
dc.type | Conference proceeding | |
dspace.entity.type | Publication | |
local.contributor.authorid | N/A | |
local.contributor.kuauthor | Taşıran, Serdar | |
relation.isOrgUnitOfPublication | 89352e43-bf09-4ef4-82f6-6f9d0174ebae | |
relation.isOrgUnitOfPublication.latestForDiscovery | 89352e43-bf09-4ef4-82f6-6f9d0174ebae |