Publication:
Automated and modular refinement reasoning for concurrent programs

dc.contributor.coauthorHawblitzel, Chris
dc.contributor.coauthorPetrank, Erez
dc.contributor.coauthorQadeer, Shaz
dc.contributor.departmentDepartment of Computer Engineering
dc.contributor.kuauthorTaşıran, Serdar
dc.contributor.kuprofileFaculty Member
dc.contributor.otherDepartment of Computer Engineering
dc.contributor.schoolcollegeinstituteCollege of Engineering
dc.contributor.yokidN/A
dc.date.accessioned2024-11-09T23:59:52Z
dc.date.issued2015
dc.description.abstractWe present CIVL, a language and verifier for concurrent programs based on automated and modular refinement reasoning. CIVL supports reasoning about a concurrent program at many levels of abstraction. Atomic actions in a high-level description are refined to fine-grain and optimized lower-level implementations. A novel combination of automata theoretic and logic-based checks is used to verify refinement. Modular specifications and proof annotations, such as location invariants and procedure pre- and post-conditions, are specified separately, independently at each level in terms of the variables visible at that level. We have implemented CIVL as an extension to the BOOGIE language and verifier. We have used CIVL to refine a realistic concurrent garbage collection algorithm from a simple high-level specification down to a highly-concurrent implementation described in terms of individual memory accesses.
dc.description.indexedbyWoS
dc.description.indexedbyScopus
dc.description.openaccessNO
dc.description.publisherscopeInternational
dc.description.volume9207
dc.identifier.doi10.1007/978-3-319-21668-3_26
dc.identifier.eissn1611-3349
dc.identifier.isbn978-3-319-21668-3
dc.identifier.isbn978-3-319-21667-6
dc.identifier.issn0302-9743
dc.identifier.quartileQ4
dc.identifier.scopus2-s2.0-84951179627
dc.identifier.urihttp://dx.doi.org/10.1007/978-3-319-21668-3_26
dc.identifier.urihttps://hdl.handle.net/20.500.14288/15715
dc.identifier.wos491470400026
dc.keywordsVerification
dc.keywordsReduction
dc.keywordsProofs
dc.languageEnglish
dc.publisherSpringer International Publishing Ag
dc.sourceComputer Aided Verification, Cav 2015, Pt II
dc.subjectComputer science
dc.subjectSoftware engineering
dc.subjectComputer science-mathematics
dc.subjectElectrical electronics engineering
dc.titleAutomated and modular refinement reasoning for concurrent programs
dc.typeConference proceeding
dspace.entity.typePublication
local.contributor.authoridN/A
local.contributor.kuauthorTaşıran, Serdar
relation.isOrgUnitOfPublication89352e43-bf09-4ef4-82f6-6f9d0174ebae
relation.isOrgUnitOfPublication.latestForDiscovery89352e43-bf09-4ef4-82f6-6f9d0174ebae

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