Publication: Computing timing jitter from phase noise spectra for oscillators and phase-locked loops with white and 1/f noise
dc.contributor.department | Department of Electrical and Electronics Engineering | |
dc.contributor.kuauthor | Demir, Alper | |
dc.contributor.schoolcollegeinstitute | College of Engineering | |
dc.date.accessioned | 2024-11-09T23:26:42Z | |
dc.date.issued | 2006 | |
dc.description.abstract | Phase noise and timing jitter in oscillators and phase-locked loops (PLLs) are of major concern in wireless and optical communications. In this paper, a unified analysis of the relationships between time-domain jitter and various spectral characterizations of phase noise is first presented. Several notions of phase noise spectra are considered, in particular, the power-spectral density (PSD) of the excess phase noise, the PSD of the signal generated by a noisy oscillator/PLL, and the so-called single-sideband (SSB) phase noise spectrum. We investigate the origins of these phase noise spectra and discuss their mathematical soundness. A simple equation relating the variance of timing jitter to the phase noise spectrum is derived and its mathematical validity is analyzed. Then, practical results on computing jitter from spectral phase noise characteristics for oscillators and PLLs with both white (thermal, shot) and 1/f noise are presented. We are able to obtain analytical timing jitter results for free-running oscillators and first-order PLLs. A numerical procedure is used for higher order PLLs. The phase noise spectrum needed for computing jitter may be obtained from analytical phase noise models, oscillator or PLL noise analysis in a circuit simulator, or from actual measurements. | |
dc.description.indexedby | WOS | |
dc.description.indexedby | Scopus | |
dc.description.issue | 9 | |
dc.description.openaccess | NO | |
dc.description.sponsoredbyTubitakEu | N/A | |
dc.description.volume | 53 | |
dc.identifier.doi | 10.1109/TCSI.2006.881184 | |
dc.identifier.eissn | 1558-0806 | |
dc.identifier.issn | 1549-8328 | |
dc.identifier.scopus | 2-s2.0-33749373005 | |
dc.identifier.uri | https://doi.org/10.1109/TCSI.2006.881184 | |
dc.identifier.uri | https://hdl.handle.net/20.500.14288/11572 | |
dc.identifier.wos | 240757000002 | |
dc.keywords | 1/f noise | |
dc.keywords | Phase-locked loops (PLLs) | |
dc.keywords | Phase noise | |
dc.keywords | Phase noise spectrum | |
dc.keywords | Timing jitter | |
dc.keywords | Oscillators | |
dc.keywords | White noise | |
dc.keywords | Model | |
dc.language.iso | eng | |
dc.publisher | IEEE-Inst Electrical Electronics Engineers Inc | |
dc.relation.ispartof | IEEE Transactions On Circuits and Systems I-Regular Papers | |
dc.subject | Engineering | |
dc.subject | Electrical electronic engineering | |
dc.title | Computing timing jitter from phase noise spectra for oscillators and phase-locked loops with white and 1/f noise | |
dc.type | Journal Article | |
dspace.entity.type | Publication | |
local.contributor.kuauthor | Demir, Alper | |
local.publication.orgunit1 | College of Engineering | |
local.publication.orgunit2 | Department of Electrical and Electronics Engineering | |
relation.isOrgUnitOfPublication | 21598063-a7c5-420d-91ba-0cc9b2db0ea0 | |
relation.isOrgUnitOfPublication.latestForDiscovery | 21598063-a7c5-420d-91ba-0cc9b2db0ea0 | |
relation.isParentOrgUnitOfPublication | 8e756b23-2d4a-4ce8-b1b3-62c794a8c164 | |
relation.isParentOrgUnitOfPublication.latestForDiscovery | 8e756b23-2d4a-4ce8-b1b3-62c794a8c164 |