Monolithic technology for silicon nanowires in high-topography architectures

Abstract

Integration of silicon nanowires (Si NWs) in three-dimensional (3D) devices including integrated circuits (ICs) and microelectromechanical systems (MEMS) leads to enhanced functionality and performance in diverse applications. The immediate challenge to the extensive use of Si NWs in modern electronic devices is their integration with the higher-order architecture. Topography-related limits of integrating Si NWs in the third dimension are addressed in this work. Utilizing a well-tuned combination of etching and protection processes, Si NWs are batch-produced in bulk Si with an extreme trench depth of 40 gm, the highest trench depth obtained in a monolithic fashion within the same Si crystal so far. The implications of the technique for the thick silicon-on-insulator (S01) technology are investigated. The process is transferred to SOI wafers yielding Si NWs with a critical dimension of 100 nm along with a trench aspect ratio of 50. Electrical measurements verify the prospect of utilizing such suspended Si NWs spanning deep trenches as versatile active components in ICs and MEMS. Introducing a new monolithic approach to obtaining Si NWs and the surrounding higher-order architecture within the same SOI wafer, this work opens up new possibilities for modem sensors and power efficient ICs. (C) 2017 Elsevier B.V. All rights reserved.