Publication:
Accurate prediction of random telegraph noise effects in srams and drams

dc.contributor.coauthorAadithya, Karthik V.
dc.contributor.coauthorVenugopalan, Sriramkumar
dc.contributor.coauthorRoychowdhury, Jaijeet
dc.contributor.departmentDepartment of Electrical and Electronics Engineering
dc.contributor.kuauthorDemir, Alper
dc.contributor.schoolcollegeinstituteCollege of Engineering
dc.date.accessioned2024-11-10T00:00:46Z
dc.date.issued2013
dc.description.abstractWith aggressive technology scaling and heightened variability, circuits such as SRAMs and DRAMs have become vulnerable to random telegraph noise (RTN). The bias dependence (i.e., non-stationarity), bi-directional coupling, and high inter-device variability of RTN present significant challenges to understanding its circuit-level effects. In this paper, we present two computer-aided design (CAD) tools, SAMURAI and MUSTARD, for accurately estimating the impact of non-stationary RTN on SRAMs and DRAMs. While traditional (stationary) analysis is often overly pessimistic (e. g., it overestimates RTN-induced SRAM failure rates), the predictions made by SAMURAI and MUSTARD are more reliable by virtue of non-stationary analysis.
dc.description.fulltextNo
dc.description.harvestedfromManual
dc.description.indexedbyWOS
dc.description.indexedbyScopus
dc.description.openaccessNO
dc.description.peerreviewstatusN/A
dc.description.publisherscopeInternational
dc.description.readpublishN/A
dc.description.sponsoredbyTubitakEuN/A
dc.description.versionN/A
dc.identifier.doi10.1109/TCAD.2012.2212897
dc.identifier.eissn1937-4151
dc.identifier.embargoN/A
dc.identifier.issn0278-0070
dc.identifier.quartileQ2
dc.identifier.scopus2-s2.0-84871746370
dc.identifier.urihttps://doi.org/10.1109/TCAD.2012.2212897
dc.identifier.urihttps://hdl.handle.net/20.500.14288/15862
dc.identifier.wos314676500007
dc.keywords1/F noise
dc.keywordsCircuit noise
dc.keywordsCircuit simulation
dc.keywordsComputational modeling
dc.keywordsComputer-aided analysis
dc.keywordsDRAM chips
dc.keywordsError probability
dc.keywordsFailure analysis
dc.keywordsSRAM chips
dc.language.isoeng
dc.publisherIEEE-Inst Electrical Electronics Engineers Inc
dc.relation.affiliationKoç University
dc.relation.collectionKoç University Institutional Repository
dc.relation.ispartofIEEE Transactions On Computer-Aided Design of Integrated Circuits and Systems
dc.relation.openaccessN/A
dc.rightsN/A
dc.subjectComputer science, hardware and architecture
dc.subjectComputer science, interdisciplinary applications
dc.subjectEngineering, electrical and electronic
dc.titleAccurate prediction of random telegraph noise effects in srams and drams
dc.typeJournal Article
dspace.entity.typePublication
local.contributor.kuauthorDemir, Alper
relation.isOrgUnitOfPublication21598063-a7c5-420d-91ba-0cc9b2db0ea0
relation.isOrgUnitOfPublication.latestForDiscovery21598063-a7c5-420d-91ba-0cc9b2db0ea0
relation.isParentOrgUnitOfPublication8e756b23-2d4a-4ce8-b1b3-62c794a8c164
relation.isParentOrgUnitOfPublication.latestForDiscovery8e756b23-2d4a-4ce8-b1b3-62c794a8c164

Files