Publication: Dual-mode floating-point multiplier architectures with parallel operations
Program
Department
School College Institute
College of Engineering
KU-Authors
KU Authors
Co-Authors
Schulte, Michael J.
Advisor
Publication Date
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Type
Embargo Status
Journal Title
Journal ISSN
Volume Title
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Abstract
Although most modern processors have hardware support for double precision or double-extended precision floating-point multiplication, this support is inadequate for many scientific computations. This paper presents the architecture of a quadruple precision floating-point multiplier that also supports two parallel double precision multiplications. Since hardware support for quadruple precision arithmetic is expensive, a new technique is presented that requires much less hardware than a fully parallel quadruple precision multiplier. With this architecture, quadruple precision multiplication has a latency of three cycles and two parallel double precision multiplications have latencies of only two cycles. The multiplier is pipelined so that two double precision multiplications can begin every cycle or a quadruple precision multiplication can begin every other cycle. The technique used for the dual-mode quadruple precision multiplier is also applied to the design of a dual-mode double precision floating-point multiplier that performs a double precision multiplication or two single precision multiplications in parallel. Synthesis results show that the dual-mode double precision multiplier requires 43% less area than a conventional double precision multiplier. The correctness of all the multipliers presented in this paper is tested and verified through extensive simulation. (c) 2006 Elsevier B.V. All rights reserved.
Source:
Publisher:
Elsevier
Subject
Computer science, Hardware architecture, Engineering, Software engineering
Citation
Has Part
Source:
Journal Of Systems Architecture
Book Series Title
Edition
DOI
10.1016/j.sysarc.2006.03.002