Publication: A dual-mode quadruple precision floating-point divider
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Abstract
Many scientific applications require more accurate computations than double precision or double-extended precision floating-point arithmetic. This paper presents the design of a dual-mode quadruple precision floating-point divider that also supports two parallel double precision division. A radix- 4 SRT division algorithm with minimal redundancy is used to implement the dual-mode quadruple precision floating-point divider. To estimate area and worst case delay, a double, a quadruple, a dual-mode double, and a dual-mode quadruple precision floating-point division units are implemented in VHDL and synthesized. The synthesis results show that the dual-mode quadruple precision divider requires 22% more area than the quadruple precision divider and the worst case delay is 1% longer. A quadruple precision division takes fifty nine cycles and two parallel double precision division take twenty nine cycles.
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IEEE
Subject
Engineering, Electrical and electronic engineering, Imaging science, Photographic technology, Telecommunications
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2006 fortieth asilomar Conference on Signals, Systems and Computers, Vols 1-5
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DOI
10.1109/aCSSC.2006.355050