Researcher:
Bayrakçı, Alp Arslan

Profile Picture
ORCID

Job Title

PhD Student

First Name

Alp Arslan

Last Name

Bayrakçı

Name

Name Variants

Bayrakçı, Alp Arslan

Email Address

Birth Date

Filters

2007 - 20102

Advanced Search

Filter by

Settings

Researcher Of Publications: search.filters.isAuthorOfPublication.78636c69-7eb9-4487-be19-99dc215c4914

Search Results

Now showing 1 - 2 of 2
  • Placeholder
    PublicationMetadata only
    Fast Monte Carlo estimation of timing yield with importance sampling and transistor-level circuit simulation
    (Ieee-Inst Electrical Electronics Engineers Inc, 2010) N/A; Department of Electrical and Electronics Engineering; Department of Computer Engineering; Bayrakçı, Alp Arslan; Demir, Alper; Taşıran, Serdar; PhD Student; Faculty Member; Faculty Member; Department of Electrical and Electronics Engineering; Department of Computer Engineering; Graduate School of Sciences and Engineering; College of Engineering; College of Engineering; N/A; 3756; N/A
    Considerable effort has been expended in the electronic design automation community in trying to cope with the statistical timing problem. Most of this effort has been aimed at generalizing the static timing analyzers to the statistical case. On the other hand, detailed transistor-level simulations of the critical paths in a circuit are usually performed at the final stage of performance verification. We describe a transistor-level Monte Carlo (MC) technique which makes final transistor-level timing verification practically feasible. The MC method is used as a golden reference in assessing the accuracy of other timing yield estimation techniques. However, it is generally believed that it can not be used in practice as it requires too many costly transistor-level simulations. We present a novel approach to constructing an improved MC estimator for timing yield which provides the same accuracy as standard MC but at a cost of much fewer transistor-level simulations. This improved estimator is based on a unique combination of a variance reduction technique, importance sampling, and a cheap but approximate gate delay model. The results we present demonstrate that our improved yield estimator achieves the same accuracy as standard MC at a cost reduction reaching several orders of magnitude.
  • Placeholder
    PublicationMetadata only
    Reduced delay BCD adder
    (IEEE, 2007) N/A; Department of Computer Engineering; Bayrakçı, Alp Arslan; Akkaş, Ahmet; PhD Student; Faculty Member; Department of Computer Engineering; Graduate School of Sciences and Engineering; College of Engineering; N/A; N/A
    Financial and commercial applications use decimal data and spend most of their time in decimal arithmetic. Software implementation of decimal arithmetic is typically at least 100 times slower than binary arithmetic implemented in hardware. therefore, hardware support for decimal arithmetic is required. in this paper, A reduced delay binary coded decimal (BCD) adder is proposed. the proposed adder improves the delay of BCD addition by increasing parallelism. on the critical-path of the proposed BCD adder, there are two 4-bit binary adders, A carry network, one and gate, and one OR gate. To make area and delay comparison, the proposed adder and previously proposed five decimal adders are implemented in VHDL and synthesized using 0.18 micron TSMC aSIC library. Synthesis results obtained for 64-bit addition (16 decimal digits) show that the proposed BCD adder has the shortest delay (1.40 ns). Furthermore, it requires less area than previously proposed three decimal adders.